IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 37

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Block Description
December 2010 Altera Corporation
Avalon-MM Slave Interface
The controller translates memory requests from the Avalon Memory-Mapped
(Avalon-MM) interface to AFI, while satisfying timing requirements imposed by the
memory configurations.
This topic describes the blocks in the IP.
RLDRAM II controller architecture.
Figure 5–1. RLDRAM II Controller Architecture Block Diagram
This Avalon-MM slave interface accepts read and write requests. A simple state
machine represents the state of the command and address registers, which stores the
command and address when a request arrives.
The Avalon-MM slave interface decomposes the Avalon-MM address to the memory
bank, column, and row addresses. The IP automatically maps the bank address to the
LSB of the Avalon address vector.
The Avalon-MM slave interface includes a burst adaptor, which has the following two
parts:
■
The first part is a read and write request combiner that groups requests to
sequential addresses into the native memory burst. Given that the second request
arrives within the read and write latency window of the first request, the
controller can combine and satisfy both requests with a single memory
transaction.
AFI to PHY
5. Functional Description—Controller
Command
Issuing
Timers
Write
FIFO
Data
Bank
FSM
with UniPHY
Controller
Figure 5–1
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Refresh
Timer
shows a block diagram of the
External Memory Interface Handbook Volume 3
Avalon-MM Slave
Interface