IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 50

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–10
UniPHY Signals
Table 6–4. Clock and Reset Signals
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
pll_ref_clk
global_reset_n
soft_reset_n
reset_request_n
seriesterminationcontrol
parallelterminationcontrol
oct_rdn
oct_rup
Name
Figure 6–7. PHY Architecture without Master for OCT Control Block
This section describes the UniPHY signals.
signals.
Memory Interface
RUP and RDN
Input
Input
Input
Output
Input (for OCT
slave)
Output(for
OCT master)
Input (for OCT
slave)
Output (for
OCT master)
Input (for OCT
master)
Input (for OCT
master)
Direction
OCT
PLL reference clock input.
Active low global reset for PLL and all logic in the PHY, which causes a
complete reset of the whole system.
Holding soft_reset_n low holds the PHY in a reset state. However it
does not reset the PLL, which keeps running. It also holds the
afi_reset_n output low. Mainly for use by SOPC Builder.
When the PLL is locked, reset_request_n is high. When the PLL is
out of lock, reset_request_n is low.
Required signal for PHY to provide series termination calibration
value. Must be connected to a user-instantiated OCT control block
(alt_oct) or another UniPHY instance that is set to OCT master
mode.
Unconnected PHY signal, available for sharing with another PHY.
Required signal for PHY to provide series termination calibration
value. Must be connected to a user-instantiated OCT control block
(alt_oct) or another UniPHY instance that is set to OCT master mode.
Unconnected PHY signal, available for sharing with another PHY.
Must connect to calibration resistor tied to GND on the appropriate
RDN pin on the device. (See appropriate device handbook.)
Must connect to calibration resistor tied to V
RUP pin on the device. (See appropriate device handbook.)
Series and Parallel
Termination Control
Buses
UniPHY Top-Level File
PLL and DLL Sharing Interface
DLL
Table 6–4
UniPHY
Description
PLL
Chapter 6: Functional Description—UniPHY
shows the clock and reset
December 2010 Altera Corporation
ccio
Reset Interface
on the appropriate
AFI
UniPHY Signals