IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 39

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Controller
Avalon-MM and Memory Data Width
Avalon-MM and Memory Data Width
Signal Description
December 2010 Altera Corporation
Error Detection Parity
User-Controlled Refresh
f
The error detection parity protection feature creates a simple parity encoder block
which processes all read and write data. The error detection feature asserts an error
signal if it detects any corrupted data during the read process. For every 8 bits of write
data, a parity bit is generated and concatenated to the data before it is written to the
memory. During the subsequent read operation, the parity bit is checked against the
data bits to ensure data integrity.
Enabling the error detection parity protection feature reduces the local data width by
one. For example, a nine-bit memory interface will present eight bits of data to the
controller interface.
You can enable error detection parity protection in the Controller Settings section of
the General Settings tab of the parameter editor.
The user-controlled refresh feature allows you to take control of the refresh process
that the controller normally performs automatically. You can control when refresh
requests occur, and, if there are multiple memory devices, you control which bank
receives the refresh signal. When you enable this feature, you disable auto-refresh,
and assume responsibility for maintaining the necessary average periodic refresh rate.
You can enable user-controlled refresh in the Controller Settings section of the
General Settings tab of the parameter editor.
Table 5–1
Avalon-MM interface. The half-rate controller does not support burst-of-2 devices
because it under-uses the available memory bandwidth.
Table 5–1. Data Width Ratio
This topic discusses the signals for each interface.
For information on the AFI signals, refer to
2-word
4-word
8-word
Memory Burst Length
shows the data width ratio between the memory interface and the
Half-Rate Designs
No Support
Section IV. RLDRAM II Controller with UniPHY IP User Guide
4:1
“UniPHY Signals” on page
External Memory Interface Handbook Volume 3
Full-Rate Designs
2:1
6–10.
5–3