IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 17

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Qsys System Integration Tool Design Flow
Qsys System Integration Tool Design Flow
December 2010 Altera Corporation
Simulate the System
f
f
f
During system generation, you can specify whether SOPC Builder generates a
simulation model and testbench for the entire system, which you can use to easily
simulate your system in any of Altera's supported simulation tools. SOPC Builder
also generates a set of ModelSim
the testbench and plain-text RTL design files that describe your system in the
ModelSim simulation software.
For information about the latest Altera-supported simulation tools, refer to the
Quartus II Software Release
For information about simulating SOPC Builder systems, refer to the
User Guide
For general information about simulating Altera IP cores, refer to
Designs
You can use the Qsys system integration tool to build a system that includes your
customized IP core. You easily can add other components and quickly create a Qsys
system. Qsys automatically generates HDL files that include all of the specified
components and interconnections. In Qsys, you specify the connections you want.
The HDL files are ready to be compiled by the Quartus II software to produce output
files for programming an Altera device. Qsys generates Verilog HDL simulation
models for the IP cores that comprise your system.
block diagram of an example Qsys system.
Figure 2–4. Example Qsys System
SDRAM
DDR3
in volume 3 of the Quartus II Handbook.
and
AN 351: Simulating Nios II Embedded Processor
Qsys System
PCIe to Ethernet Bridge
PHY
Cntl
Notes.
Controller
SDRAM
DDR3
®
Slave
Mem
Tcl scripts and macros that you can use to compile
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Mem
Mstr
Mem
Mstr
PCI Express
Subsystem
Subsystem
Ethernet
Figure 2–4
External Memory Interface Handbook Volume 3
CSR
CSR
Designs.
shows a high level
Simulating Altera
Embedded Cntl
Ethernet
SOPC Builder
PCIe
2–7