IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 25

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Generated Files
Table 2–7. Generated Directory Structure and Key Files—MegaWizard Plug-In Manager Example Design (Part 2 of 2)
Table 2–8. Generated Directory Structure and Key Files—SOPC Builder Flow (Part 1 of 2)
December 2010 Altera Corporation
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/example
_project/
<working_dir>/<variation_name>
_example_design_fileset/rtl_sim/
Note to
(1) <prefix> varies depending on protocol and type of memory model.
<working_dir>/
<working_dir>/
<working_dir>/
<working_dir>/
<working_dir>/
<working_dir>/
Table
SOPC Builder Flow
Directory
Directory
2–7:
Table 2–8
Builder flow.
lists the generated directory structure and key files created by the SOPC
<variation_name>.ppf
<variation_name>_pin_assignments.tcl
<variation_name>_*.tcl
<variation_name>_readme.txt
<variation_name>_example_top.qpf
<variation_name>_example_top.qsf
<variation_name>_example_top.v
<variation_name>_*.v
<variation_name>_*.sv
<prefix>_mem_model.sv
<variation_name>_example_top_tb.v
<system_name>.qip
<system_name>.v
<core_name>_<stamp>.v
<core_name>_<stamp>_*.v
<core_name>_<stamp>_*.sv
<core_name>_<stamp>.sdc
File Name‘
File Name‘
(1)
(1)
(1)
(1)
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
Pin Planner file.
Pin constraints script to be run
after synthesis.
Other Tcl scripts.
Readme text file.
Example design project file.
Example design project settings
file.
Top-level wrapper including
UniPHY, traffic generator, and
memory model.
Other example design Verilog RTL
files.
Other example design
SystemVerilog RTL files.
Generic memory model.
Top-level test bench.
QIP which refers to all generated
files in the SOPC Builder project.
SOPC Builder system top-level
wrapper.
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL files.
Synopsys constraints file.
Description
Description
2–15