IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 53

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
UniPHY Signals
Table 6–8. Top-Level HardCopy Migration Signals (Part 2 of 2)
December 2010 Altera Corporation
hc_rom_config_init_busy
hc_rom_config_rom_rden
hc_rom_config_rom_address
DLL Reconfiguration Signals
hc_dll_config_dll_offset_ctrl_addnsub
hc_dll_config_offset_ctrl_offset
hc_dll_config_dll_offset_ctrl_offsetctrlout
PLL Reconfiguration Signals
hc_pll_config_configupdate
hc_pll_config_phasecounterselect
hc_pll_config_phasestep
hc_pll_config_phaseupdown
hc_pll_config_scanclk
hc_pll_config_scanclkena
hc_pll_config_scandata
hc_pll_config_scandataout
hc_pll_config_scandone
Name
Output
Output
Output
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Output
Output
Direction
Section IV. RLDRAM II Controller with UniPHY IP User Guide
When asserted, indicates ROM loading is
in progress. The soft_reset_n signal
should be de-asserted if the ROM data is
not loaded, and also when the ROM is
being loaded. The falling edge of
hc_rom_config_init_busy indicates the
completion of the ROM loading process, at
which time, soft_reset_n can be asserted.
Read-enable signal that connects to the
external ROM.
ROM address that connects to the external
ROM.
Addition and subtraction control port for
the DLL. This port controls if the
delay-offset setting on hc_dll_config_
dll_offset_ctrl_offset is added or
subtracted.
Offset input setting for the DLL. This
setting is a Gray-coded offset that is added
or subtracted from the current value of the
DLL’s delay chain.
The registered and Gray-coded value of the
current delay-offset setting.
Control signal to enable PLL
reconfiguration.
Specifies the counter select for dynamic
phase adjustment.
Specifies the phase step for dynamic
phase shifting.
Specifies whether the phase shift is up or
down.
PLL reconfiguration scan chain clock.
Clock enable port of the
hc_pll_config_scanclk clock.
Serial input data for the PLL
reconfiguration scan chain.
Data output of the serial scan chain.
This signal is asserted when the scan
chain write operation is in progress. This
signal is deasserted when the write
operation is complete.
External Memory Interface Handbook Volume 3
Description
6–13