IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 72

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

9–2
Figure 9–2. Back-to-Back Reads
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
1
Figure 9–2
You can set the avl_size to 0x2 and hold avl_addr constant at 0x0 to perform the
same back-to-back read.
Figure 9–3
Figure 9–3. Refresh to Bank 0
shows back-to-back read from addresses 0 and 1.
shows refresh to bank 0.
December 2010 Altera Corporation
Chapter 9: Timing Diagrams