IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 61

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Using a Custom Controller
Using a Custom Controller
Using a Vendor-Specific Memory Model
December 2010 Altera Corporation
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The UniPHY-based memory interface IP cores integrate the PHY and the memory
controller. To replace the Altera high-performance memory controller with a custom
memory controller, perform the following steps:
1. Parameterize and generate your variation of the UniPHY-based memory controller
2. Open the <variation_name>/<variation_name>_<stamp>_controller_phy.sv file.
3. Replace the <variation_name>_<stamp>_alt_rld_controller module with your
4. Delete the ports of the Altera high-performance memory controller, and add the
5. Similarily, update the port names in the top-level module in the
6. Compile and simulate the design to confirm correct operation.
Regenerating the UniPHY memory interface IP erases all modifications made to the
HDL files. The parameters you select in the parameter editor are stored in the
top-level <variation_name> module; hence, you must repeat the above steps every
time you regenerate the IP variation.
For half-rate controllers, AFI signals are double the bus width of the memory
interface. Half rate controllers have double the width of the signal and run at half the
speed. Hence, the overall bandwidth is maintained. Such double-width signals are
divided into two signals for transmission to the memory interface, with a higher order
bits representing the most-significant bit (MSB) and a lower order bits representing
the least-significant bit (LSB). The LSB is transmitted first, and is followed by the MSB.
You can replace the Altera-supplied memory model with a vendor-specific memory
model. In general, you may find vendor-specific models to be standardized, thorough,
and well supported, but sometimes more complex to setup and use.
If you do want to replace the Altera-supplied memory model with a vendor-supplied
memory model, observe the following guidelines:
IP as described in
This step creates a top-level HDL file called <variation_name>.v (or
<variation_name>.vhd), and a sub-directory called <variation_name>.
The top-level module instantiates the <variation_name>_<stamp>_controller_phy
module in the <variation_name> subdirectory. The
<variation_name>_<stamp>_controller_phy module instantiates the PHY and the
controller.
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custom controller module.
top-level ports of your custom controller.
<variation_name>.v or <variation_name>.vhd file.
<stamp> is a unique identifier determined by the MegaWizard Plug-in
Manager, SOPC Builder, or Qsys, during generation.
“Getting Started” on page
Section IV. RLDRAM II Controller with UniPHY IP User Guide
2–1.
External Memory Interface Handbook Volume 3
6–21