IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 52

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–12
Table 6–6. Sideband Signals
Table 6–7. RLDRAM II Interface Signals
Table 6–8. Top-Level HardCopy Migration Signals (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
oct_ctl_rs_value
oct_ctl_rt_value
mem_a
mem_ba
mem_ck, mem_ck_n
mem_dk, mem_dkn
mem_dm
mem_dq
mem_ref_n
mem_qk, mem_qk_n
mem_we_n
altsyncram Signals
hc_rom_config_clock
hc_rom_config_datain
hc_rom_config_rom_data_ready
hc_rom_config_init
Signal name
Name
Table 6–6
Table 6–7
Table 6–8
Input
Input
Direction
Name
shows the sideband signals.
shows the RLDRAM II interface signals.
shows the top-level signals generated for HardCopy migration.
Output
Output
Output
Output
Output
Bidirectional
Output
Input
Output
Direction
OCT_SERIES_TERM_CONTROL_WIDTH
OCT_PARALLEL_TERM_CONTROL_WIDTH
MEM_ADDRESS_WIDTH
MEM_CONTROL_WIDTH
1
MEM_WRITE_DQS_
WIDTH
MEM_DM_WIDTH
MEM_DQ_WIDTH
MEM_CONTROL_WIDTH
MEM_READ_DQS_
WIDTH
MEM_CONTROL_WIDTH
Width
Width
Input
Input
Input
Input
Direction
Address.
Bank address.
Address and command clock to memory.
Write clock(s) to memory, 1 clock per DQS
group.
Data mask.
Input and output data bus.
Connecting this pin to ground turns off the
DLL inside the device.
Read clock(s) from memory, 1 clock per
DQS group
Write enable.
Write clock for the ROM loader. This clock
is used as the write clock of the Nios II
code memory.
Data input from external ROM.
Asserts to the code memory loader that
the word memory is ready to be loaded.
Triggers the ROM loading process. Should
be asserted for one hc_rom_config_clock
cycle after PLL is locked.
Chapter 6: Functional Description—UniPHY
OCT Rs value port for use
with ALTOCT megafunction.
OCT Rt value port for use
with ALTOCT megafunction.
December 2010 Altera Corporation
Description
Description
Description
UniPHY Signals