IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 46

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–6
Table 6–3. Sequencer States (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
State
RESET
LOAD_INIT
STABLE
WRITE_ZERO
WAIT_WRITE_ZERO
WRITE_ONE
WAIT_WRITE_ONE
Valid Calibration States
V_READ_ZERO
V_READ_NOP
V_READ_ONE
V_WAIT_READ
V_COMPARE_READ_ZER
O_READ_ONE
V_CHECK_READ_FAIL
V_ADD_FULL_RATE
V_ADD_HALF_RATE
V_READ_FIFO_RESET
V_CALIB_DONE
Latency Calibration States
L_READ_ONE
L_WAIT_READ
L_COMPARE_READ_ONE
L_REDUCE_LATENCY
L_READ_FLUSH
L_WAIT_READ_FLUSH
Sequencer
The sequencer is a state machine that processes the calibration algorithm. The
sequencer assumes control of the interface at reset (whether at initial startup or when
the IP is reset) and maintains control throughout the calibration process, relinquishing
control to the memory controller only after successful calibration.
major states in the sequencer.
Description
Remain in this state until reset is released.
Load any initialization values for simulation purposes.
Wait until the memory device is stable.
Issue write command to address 0.
Write all 0s to address 0.
Issue write command to address 1.
Write all 1s to address 1.
Issue read command to address 0 (expected data is all 0s).
This state represents the minimum number of cycles required between 2 back-to-back read
commands. The number of NOP states depends on the burst length.
Issue read command to address 1 (expected data is all 1s).
Wait for read valid signal.
Parameterizable number of cycles to wait before making the read data comparisons.
When a read fails, the write pointer (in the AFI clock domain) of the valid FIFO buffer is
incremented. The read pointer of the valid FIFO buffer is in the DQS clock domain. The gap
between the read and write pointers is effectively the latency between the time when the PHY
receives the read command and the time valid data is returned to the PHY.
Advance the read valid FIFO buffer write pointer by an extra full rate cycle.
Advance the read valid FIFO buffer write pointer by an extra half rate cycle. In full-rate designs,
equivalent to V_ADD_FULL_RATE.
Reset the read and write pointers of the read data synchronization FIFO buffer.
Valid calibration is successful.
Issue read command to address 1 (expected data is all 1s).
Wait for read valid signal from read datapath. Initial read latency is set to a predefined
maximum value.
Check returned read data against expected data. If data is correct, go to L_REDUCE_LATENCY;
otherwise go to L_ADD_MARGIN.
Reduce the latency counter by 1.
Read from address 0 (expected data is all 0s), to flush the contents of the read data
resynchronization FIFO buffer.
Wait until the whole FIFO buffer is flushed, then go back to L_READ and try again.
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
Table 6–3
Block Description
shows the