IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 21

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
HardCopy Migration Design Guidelines
December 2010 Altera Corporation
f
Table 2–1. Top-level Ports that Connect to External ROM for Loading Nios II Code Memory (Part
2 of 2)
PLL/DLL Run-time Reconfiguration
The PLLs and DLLs in the HardCopy design have run-time reconfiguration enabled—
provided that they are not in PLL/DLL slave mode.
When the PLLs and DLLs are generated with reconfiguration enabled, there are extra
signals that must be connected and driven by user logic. In the example design
generated during IP core generation, the PLL/DLL reconfiguration signals are
brought to the top level and connected to constants, as shown in
For information about PLL megafunctions and reconfiguration, refer to the
Phase-Locked Loop (ALTPLL) Megafunction User Guide
Reconfiguration (ALTPLL_RECONFIG) Megafunctions User
Figure 2–5. HardCopy UnIPHY Example Design
Table 2–2
Controller+PHY.
Table 2–2. DLL Reconfiguration Ports Exposed at Top-Level of Controller+PHY Wrapper (Part 1 of
hc_rom_config_rom_rden
hc_rom_config_rom_address
hc_dll_config_dll_offset_ctrl_
addnsub
Memory
summarizes the DLL reconfiguration ports exposed at the top level of the
Port Name
Port Name
Interface
Loader
Controller+PHY Wrapper
ROM
PHY
AFI
HardCopy Example Design
Output
Output
Controller
Input
Direction
Direction
MM-Slave
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Addition/subtraction control port for the DLL.
This port controls if the delay-offset setting on
hc_dll_config_dll_offset_ctrl_offset is added
or subtracted.
Avalon MM
Read-enable signal that connects to the
external ROM.
ROM address that connects to the
external ROM.
External Memory Interface Handbook Volume 3
and the
Reconfiguration
Interface
Guide.
PLL/DLL
MM-Master
Description
Driver
Phase-Locked Loops
Description
Figure
2–5.
Pass/Fail
2–11