CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 26

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

26
4.4
Analog Outputs
Referenced Control
DSP
PDN_DSP
DEEMPH
PMIXxMUTE
PMIXxVOL[6:0]
INV_PCMx
PCMxSWAP[1:0]
AMIXxMUTE
AMIXxVOL[6:0]
ADCxSWAP[1:0]
MSTxVOL[7:0]
MSTxMUTE
DIGSFT
PLYBCKB=A
TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
BASS[3:0]
TREB[3:0]
Limiter
LIMIT
LIMIT_ALL
LIMSRDIS
LMAX[2:0]
CUSH[2:0]
LIMARATE[7:0]
LIMRRATE[7:0]
Beep Generator
INPUTS FROM ADCA
Digital Mix to ADC
Serial Interface
and ADCB
DEEMPH
Demph
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
BEEP[1:0]
Register Location
“Power Down DSP” on page 50
“HP/Line De-Emphasis” on page 50
“PCM Mixer Channel x Mute” on page 52
“PCM Mixer Channel x Volume” on page 52
“Invert PCM Signal Polarity” on page 51
“PCM Mix Channel Swap” on page 60
“ADC Mixer Channel x Mute” on page 51
“ADC Mixer Channel x Volume” on page 51
“ADC Mix Channel Swap” on page 60
“Master Volume Control” on page 57
“Master Playback Mute” on page 51
“Digital Soft Ramp” on page 46
“Playback Channels B=A” on page 50
“Tone Control Enable” on page 56
“Bass Corner Frequency” on page 56
“Treble Corner Frequency” on page 55
“Bass Gain” on page 56
“Treble Gain” on page 56
“Peak Detect and Limiter” on page 61
“Peak Signal Limit All Channels” on page 61
“Limiter Soft Ramp Disable” on page 66
“Limiter Maximum Threshold” on page 60
“Limiter Cushion Threshold” on page 61
“Limiter Attack Rate” on page 62
“Limiter Release Rate” on page 62
Refer to
PMIXAMUTE
PMIXBMUTE
PMIXAVOL[6:0]
PMIXBVOL[6:0]
INV_PCMA
INV_PCMB
VOL
AMIXAMUTE
AMIXBMUTE
AMIXAVOL[6:0]
AMIXBVOL[6:0]
“Beep Generator” on page 31
Figure 12. DSP Engine Signal Flow
Generator
Beep
VOL
PCMASWAP[1:0]
PCMBSWAP[1:0]
Channel
*
Swap
Fixed Function DSP
BPVOL[4:0]
VOL
Channel
MSTxVOL[7:0], MSTxMUTE and DIGSFT are always
available regardless of the PDN_DSP setting.
Swap
Σ
MSTAVOL[7:0]
MSTBVOL[7:0]
ADCASWAP[1:0]
ADCBSWAP[1:0]
for all referenced controls
Chnl Vol.
Settings
Σ
MSTAMUTE
MSTBMUTE
DIGSFT
PLYBCKB=A
VOL
TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
BASS[3:0]
TREB[3:0]
Control
Treble/
Bass/
LIMARATE[7:0]
LIMRRATE[7:0]
LMAX[2:0]
CUSH[2:0]
LIMSRDIS
LIMIT
LIMIT_ALL
PDN_DSP
Limiter
Detect
Peak
*
DAC
CS42L55
DS773F1
to HP and
Line MUX