CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 44

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

44
6.4.3
6.4.4
6.4.5
6.5
6.5.1
Reserved
7
Clocking Control 2 (Address 05h)
SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
MCLK Divide By 2
Configures a divide of the input MCLK prior to all internal circuitry.
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
Note:
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
SCK=MCK[1:0]
00
01
10
11
MCLKDIV2
0
1
Application:
MCLKDIS
0
1
SPEED[1:0]
00
01
10
11
Application:
(“32 kHz Sample Rate Group” on page
page
Refer to the referenced application for more information.
Reserved
This function should be enabled during power down (PDN=1) ONLY.
45). Low sample rates may also affect dynamic range performance in the typical audio band.
6
Output SCLK
Re-timed, bursted signal with minimal speed needed to clock the required data samples
Reserved
MCLK signal after the MCLK divide (MCLKDIV2) circuit
MCLK signal before the MCLK divide (MCLKDIV2) circuit
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
MCLK signal into CODEC
On
Off; Disables the clock tree to save power when the CODEC is powered down.
Serial Port Speed
Reserved
Single-Speed Mode (SSM)
Half-Speed Mode (HSM)
Quarter-Speed Mode (QSM)
“Serial Port Clocking” on page 34
Reserved
5
SPEED1
4
45) and the RATIO[1:0] bits
SPEED0
3
“Master/Slave Mode” on page
32kGROUP
2
(“Internal MCLK/LRCK Ratio” on
RATIO1
1
43.
CS42L55
RATIO0
DS773F1
0