CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 64

Eval Bd Ultra Low Power Stereo Codec

CDB42L55

Manufacturer Part Number
CDB42L55
Description
Eval Bd Ultra Low Power Stereo Codec
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42L55

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42L55
Primary Attributes
2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
Secondary Attributes
GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1506
CDB-42L55
64
6.31
6.31.1 ALC Maximum Threshold
6.31.2 ALC Minimum Threshold
6.32
6.32.1 Noise Gate All Channels
ALCMAX2
NGALL
7
7
ALC Threshold (Address 26h)
Noise Gate Control (Address 27h)
Sets the maximum level, below full-scale, at which to limit and attenuate the input signal at the attack rate
(ALCARATE -
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the re-
lease rate (ALCRRATE -
CMIN thresholds.
Note:
Sets which channels are attenuated when clipping on any single channel occurs.
MAX[2:0]
000
001
010
011
100
101
110
111
Application:
ALCMIN[2:0]
000
001
010
011
100
101
110
111
Application:
NGALL
0
1
ALCMAX1
This setting is usually set slightly below the ALCMAX threshold.
NG
6
6
“ALC Attack Rate” on page
Threshold Setting
0 dB
-3 dB
-6 dB
-9 dB
-12 dB
-18 dB
-24 dB
-30 dB
Threshold Setting
0 dB
-3 dB
-6 dB
-9 dB
-12 dB
-18 dB
-24 dB
-30 dB
Noise Gate triggered by:
Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for
ONLY that channel.
Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to
take effect.
“Automatic Level Control (ALC)” on page 24
“Automatic Level Control (ALC)” on page 24
NG_BOOST
ALCMAX0
5
5
“ALC Release Rate” on page
THRESH2
ALCMIN2
4
4
63).
THRESH1
ALCMIN1
3
3
63) until levels lie between the ALCMAX and AL-
THRESH0
ALCMIN0
2
2
NGDELAY1
Reserved
1
1
CS42L55
NGDELAY0
Reserved
DS773F1
0
0

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