CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 36

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

36
4.11.1 Recommended Power-Down Sequence
4.12
4.12.1 Recommended Power-Down Sequence
Recommended PGA to HP or Line Power-Up Sequence (Analog Passthrough)
1. Hold RESET low until the power supplies are stable; no specific power supply sequencing is required.
2. Apply MCLK at the appropriate frequency.
3. Bring RESET high.
4. Wait a minimum of 500 ns before writing to the control port.
5. The default state of the master power down bit, PDN, is ‘1’b. Load the following register settings while
6. Load the required register settings detailed in
7. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation.
8. Configure the HP and/or Line amplifiers to receive the analog output from the PGA.
9. Power down the DSP engine.
10. To minimize pops on the headphone or line amplifier, each respective analog volume control must first
11. After muting the headphone and/or line amplifiers, set the PDN bit to ‘0’b.
12. Wait 75 ms for the headphone or line amplifier to power up.
13. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level.
14. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
Power Up Sequence
Step 5,
Step
Steps
Step
Step 10a,13a .......................
Step 10b,13b .......................
Power Down Sequence
Step 1a ................................
Step 1b ................................
Step
1. To minimize pops on the headphone or line amplifier, each respective analog volume control must
2. Set the PDN bit to ‘1’b.
3. Bring RESET low.
1. To minimize pops on the headphone and/or line amplifier, each respective analog volume control
2. During power down, the CODEC attempts to power down on a zero cross transition of the analog
RESET should be held low for a minimum of 1 ms after power supplies are stable.
keeping the PDN bit set to ‘1’b.
Register Controls: PDN_HPx[1:0], PDN_LINx[1:0]
Register Controls: LINExMUX, HPxMUX
Register Controls: PDN_DSP
be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
prevent power glitch related issues.
7
9
2
8
..................................
..................................
first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
must first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
..................................
11
................................
............................
Register Location
“Power Down” on page 42
“Power Control 2 (Address 03h)” on page 43
“ADC, Line, HP MUX (Address 08h)” on page 46
“Power Down DSP” on page 50
“Headphone Channel x Mute” on page
“Headphone Volume Control” on page
Register Location
“Headphone Volume Control” on page
“Headphone Channel x Mute” on page
“Power Down” on page 42
4.13 “Required Initialization Settings” on page
57,
57,
57,
57,
“Line Volume Control” on page 58
“Line Volume Control” on page 58
“Line Channel x Mute” on page 58
“Line Channel x Mute” on page 58
CS42L55
37.
DS773F1