CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 45

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

DS773F1
6.5.2
6.5.3
6.6
6.6.1
6.7
6.7.1
Reserved
DIGMUX
7
7
Class H Power Control (Address 06h)
Miscellaneous Control (Address 07h)
32 kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
Adaptive Power Adjustment
Configures how the power to the headphone and line amplifiers adapts to the output signal level.
Digital MUX
Selects the signal source for the ADC serial port.
32kGROUP
0
1
Application:
RATIO[1:0]
00
01
10
11
Application:
ADPTPWR[1:0]
00
01
10
11
Application:
DIGMUX
0
1
Reserved
Reserved
6
6
8 kHz, 16 kHz or 32 kHz sample rate?
No
Yes
“Serial Port Clocking” on page 34
Internal MCLK Cycles per LRCK
Reserved
125
Reserved
136
“Serial Port Clocking” on page 34
Power Supply
Adapted to volume setting; Voltage level is determined by the sum of the relevant volume settings
Fixed - Headphone and Line Amp supply = +/-VCP/2
Fixed - Headphone and Line Amp supply = +/-VCP
Adapted to Signal; Voltage level is dynamically determined by the output signal
“Class H Amplifier” on page 27
SDOUT Signal Source
ADC
DSP Mix
ADPTPWR1
Reserved
5
5
ADPTPWR0
Reserved
4
4
Reserved
ANLGZC
3
3
Reserved
DIGSFT
2
2
Reserved
Reserved
1
1
CS42L55
Reserved
FREEZE
0
0
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