CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 42

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

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6. REGISTER DESCRIPTION
Except for the chip I.D., revision register, and status register, which are Read Only, all registers are Read/Write. See
the following bit definition tables for bit assignment information. The default state of each bit after a power-up se-
quence or reset is listed in each bit description. All Reserved registers must maintain their default state.
6.1
6.1.1
6.2
6.2.1
6.2.2
6.2.3
I²C Address: 1001010[R/W]
Reserved
Reserved
7
7
Fab I.D. and Revision Register (Address 01h) (Read Only)
Power Control 1 (Address 02h)
Chip Revision (Read Only)
CS42L55 revision level.
Power Down ADC Charge Pump
Configures the power state of the ADC charge pump. For optimal ADC performance and power consump-
tion, set to ‘1’b when VA > 2.1 V and set to ‘0’b when VA < 2.1 V.
Power Down ADC x
Configures the power state of ADC channel x.
Power Down
Configures the power state of the entire CODEC.
REVID[2:0]
000
001
PDN_CHRG
0
1
PDN_ADCx
0
1
PDN
0
1
Reserved
Reserved
6
6
Revision Level
A0
A1
ADC Charge Pump Status
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ADC Status
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CODEC Status
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Reserved
Reserved
5
5
Reserved
Reserved
4
4
PDN_CHRG
Reserved
3
3
PDN_ADCB
REVID2
2
2
PDN_ADCA
REVID1
1
1
CS42L55
REVID0
DS773F1
PDN
0
0