ADSP-TS101SAB2-000 Analog Devices Inc, ADSP-TS101SAB2-000 Datasheet - Page 17

IC,DSP,32-BIT,BGA,484PIN,PLASTIC

ADSP-TS101SAB2-000

Manufacturer Part Number
ADSP-TS101SAB2-000
Description
IC,DSP,32-BIT,BGA,484PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
TigerSHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-TS101SAB2-000

Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Multi-Processor
Clock Rate
250MHz
Non-volatile Memory
External
On-chip Ram
768kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
484-BGA
Package
484BGA
Numeric And Arithmetic Format
Fixed-Point|Floating-Point
Maximum Speed
250 MHz
Ram Size
768 KB
Device Million Instructions Per Second
250 MIPS
Lead Free Status / RoHS Status
Other names
ADSP-TS101SAB2000

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-TS101SAB2-000
Manufacturer:
MINI
Quantity:
1 400
Part Number:
ADSP-TS101SAB2-000
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Table 9. Pin Definitions—JTAG Port (Continued)
1
2
3
Table 10. Pin Definitions—Flags, Interrupts, and Timer
1
2
3
Table 11. Pin Definitions—Link Ports
Signal
TDO
TMS
TRST
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k
Term (for termination) column symbols: epd = external pull-down approximately 10 k
to V
See the reference
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
See
Signal
FLAG3–0
IRQ3–0
TMR0E
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k
Term (for termination) column symbols: epd = external pull-down approximately 10 k
to V
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
See
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Signal
L0DAT7–0
L1DAT7–0
L2DAT7–0
L3DAT7–0
L0CLKOUT
L1CLKOUT
L2CLKOUT
L3CLKOUT
L0CLKIN
L1CLKIN
L2CLKIN
L3CLKIN
L0DIR
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k
Term (for termination) column symbols: epd = external pull-down approximately 10 k
to V
Electrical Characteristics on Page 20
Electrical Characteristics on Page 20
DD-IO
DD-IO
DD-IO
2
2
1
3
, nc = not connected; au = always used.
, nc = not connected; au = always used.
, nc = not connected; au = always used.
1
1
1
1
1
Page 11
to the JTAG emulation technical reference EE-68.
Type
O/T
I (pu
I/A (pu
Type
I/O/A (pd
I/A (pu
O (pd
Type
I/O
I/O
I/O
I/O
O
O
O
O
I/A
I/A
I/A
I/A
O
3
)
2
)
3
2
)
)
2
)
for maximum and minimum current consumption for pull-up and pull-down resistances.
for maximum and minimum current consumption for pull-up and pull-down resistances.
Term
nc
nc
au
Term
nc
nc
au
Term
nc
nc
nc
nc
nc
nc
nc
nc
nc
epu
epu
epu
epu
1
1
Description
Test Data Output (JTAG). A serial data output of the scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after
power-up for proper device operation.
Description
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be
configured individually for input or for output. FLAG3–0 are inputs after power-up and reset.
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins can
be independently set for edge triggered or level sensitive operation. After reset, these pins are
disabled unless the IRQ3–0 strap option is initialized for booting.
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires. At reset this
is a strap pin. For additional information, see
Description
Link0 Data 7–0
Link1 Data 7–0
Link2 Data 7–0
Link3 Data 7–0
Link0 Clock/Acknowledge Output
Link1 Clock/Acknowledge Output
Link2 Clock/Acknowledge Output
Link3 Clock/Acknowledge Output
Link0 Clock/Acknowledge Input
Link1 Clock/Acknowledge Input
Link2 Clock/Acknowledge Input
Link3 Clock/Acknowledge Input
Link0 Direction. (0 = input, 1 = output)
; pu = internal pull-up approximately 100 k
; pu = internal pull-up approximately 100 k
; pu = internal pull-up approximately 100 k
Rev. C | Page 17 of 48 | May 2009
to V
to V
to V
Table 16 on Page
; T = three-state
; T = three-state
; T = three-state
SS
SS
SS
; epu = external pull-up approximately 10 k
; epu = external pull-up approximately 10 k
; epu = external pull-up approximately 10 k
19.
ADSP-TS101S

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