ADSP-TS101SAB2-000 Analog Devices Inc, ADSP-TS101SAB2-000 Datasheet - Page 23

• Manufacturer Part Number: ADSP-TS101SAB2-000
• Description: IC,DSP,32-BIT,BGA,484PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: TigerSHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-TS101SAB2-000

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Multi-Processor
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 768kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Package: 484BGA
• Numeric And Arithmetic Format: Fixed-Point|Floating-Point
• Maximum Speed: 250 MHz
• Ram Size: 768 KB
• Device Million Instructions Per Second: 250 MIPS
• Other names: ADSP-TS101SAB2000

Table 22. Reference Clocks—System Clock (SCLK) Cycle Time
1
2
3
4
5
6
Table 23. Reference Clocks—Test Clock (TCK) Cycle Time
Table 24. Power-Up Timing
1
Parameter
t
t
t
t
For more information, see
For more information, see Clock Domains on Page 9.
LCLK_P and SCLK_P must be connected to the same source.
The value of (t
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Parameter
t
t
t
Parameter
Timing Requirement
t
For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.
SCLK
SCLKH
SCLKL
SCLKJ
TCK
TCKH
TCKL
VDD_IO
1, 2, 3, 4
5, 6
V
V
DD_IO
DD_A
V
SCLK
SCLK_P
DD
SCLK_P
TCK
/ LCLKRAT2-0) must not violate the specification for t
Description
System Clock Cycle Time
System Clock Cycle High Time
System Clock Cycle Low Time
System Clock Jitter Tolerance
Description
Test Clock (JTAG) Cycle Time
Test Clock (JTAG) Cycle High Time
Test Clock (JTAG) Cycle Low Time
V
Are Stable and Within Specification
DD_IO
Table 3 on Page
Stable and Within Specification After V
t
VDD_IO
1
12.
Figure 11. Reference Clocks—System Clock (SCLK) Cycle Time
t
Figure 12. Reference Clocks—Test Clock (TCK) Cycle Time
TCKH
t
t
SCLKH
SCLKH
Figure 13. Power-Up Sequencing Timing
t
TCK
t
t
Rev. C | Page 23 of 48 | May 2009
SCLK
SCLK
t
TCKL
t
t
SCLKL
SCLKL
CCLK
.
DD
and V
DD_A
Min
Greater of 30 or t
12.5
12.5
Min
>0
t
t
SCLKJ
SCLKJ
CCLK
× 4
Min
10
0.4 × t
0.4 × t
Max
Max
SCLK
SCLK
Max
25
0.6 × t
0.6 × t
500
ADSP-TS101S
SCLK
SCLK
Unit
ns
ns
ns
ps
Unit
ns
ns
ns
Unit
ms