ADSP-TS101SAB2-000 Analog Devices Inc, ADSP-TS101SAB2-000 Datasheet - Page 4

• Manufacturer Part Number: ADSP-TS101SAB2-000
• Description: IC,DSP,32-BIT,BGA,484PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: TigerSHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-TS101SAB2-000

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Multi-Processor
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 768kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Package: 484BGA
• Numeric And Arithmetic Format: Fixed-Point|Floating-Point
• Maximum Speed: 250 MHz
• Ram Size: 768 KB
• Device Million Instructions Per Second: 250 MIPS
• Other names: ADSP-TS101SAB2000

ADSP-TS101S
The ADSP-TS101S, in most cases, has a two-cycle arithmetic
execution pipeline that is fully interlocked, so whenever a com-
putation result is unavailable for another operation dependent
on it, the DSP automatically inserts one or more stall cycles as
needed. Efficient programming with dependency-free instruc-
tions can eliminate most computational and memory transfer
data dependencies.
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations. The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
DUAL COMPUTE BLOCKS
The ADSP-TS101S has compute blocks that can execute com-
putations either independently or together as a SIMD engine.
The DSP can issue up to two compute instructions per compute
block each cycle, instructing the ALU, multiplier, or shifter to
perform independent, simultaneous operations.
The compute blocks are referred to as X and Y in assembly syn-
tax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter, and a 32-word register file.
REFERENCE
CLK
ADDR
DATA
(OPTIONAL)
(OPTIONAL)
DEVICES
CLOCK
(4 MAX)
MEMORY
Figure 2. Single-Processor System with External SDRAM
SDRAM
LINK
DQM
RAS
CAS
CKE
A10
WE
CS
LCLK_P
SCLK_P
S/LCLK_N
V
IRQ3–0
FLAG3–0
ID2–0
MSSD
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
FLYBY
IOEN
LXDAT7–0
LXCLKIN
LXCLKOUT
LXDIR
BM
BUSLOCK
CONTROLIMP2–0
LCLKRAT2–0
SCLKFREQ
RAS
DS2–0
TMR0E
ADSP-TS101S
REF
RESET
ADDR31–0
DATA63–0
WRH/WRL
DMAR3–0
BR7–0
MS1–0
BOFF
BRST
JTAG
BMS
MSH
HBG
CPA
DPA
HBR
ACK
RD
Rev. C | Page 4 of 48 | May 2009
DATA
ADDR
DATA
ADDR
DATA
CS
ADDR
DATA
OE
WE
ACK
(OPTIONAL)
CS
PROCESSOR
DMA DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
INTERFACE
MEMORY
EPROM
BOOT
HOST
Using these features, the compute blocks can:
DATA ALIGNMENT BUFFER (DAB)
The DAB is a quad word FIFO that enables loading of quad
word data from nonaligned addresses. Normally, load instruc-
tions must be aligned to their data size so that quad words are
loaded from a quad-aligned address. Using the DAB signifi-
cantly improves the efficiency of some applications, such as FIR
filters.
DUAL INTEGER ALUS (IALUS)
The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many general-pur-
pose integer operations. Each of the IALUs:
As address generators, the IALUs perform immediate or indi-
rect (pre- and post-modify) addressing. They perform modulus
and bit-reverse operations with no constraints placed on mem-
ory addresses for the modulus data buffer placement. Each
IALU can specify either a single, dual, or quad word access from
memory.
• Register file—each compute block has a multiported
• ALU—the ALU performs a standard set of arithmetic oper-
• Multiplier—the multiplier performs both fixed- and float-
• Shifter—the 64-bit shifter performs logical and arithmetic
• Accelerator—128-bit unit for trellis decoding (for example,
• Provide 8 MACs per cycle peak and 7.1 MACs per cycle
• Execute six single-precision, floating-point or execute 24
• Perform two complex 16-bit MACs per cycle
• Execute eight trellis butterflies in one cycle
• Provides memory addresses for data and update pointers
• Supports circular buffering and bit-reverse addressing
• Performs general-purpose integer operations, increasing
• Includes a 31-word register file for each IALU
32-word, fully orthogonal register file used for transferring
data between the computation units and data buses and for
storing intermediate results. Instructions can access the
registers in the register file individually (word aligned), or
in sets of two (dual aligned) or four (quad aligned).
ations in both fixed- and floating-point formats. It also
performs logic operations.
ing-point multiplication and fixed-point multiply and
accumulate.
shifts, bit and bit stream manipulation, and field deposit
and extraction operations.
Viterbi and turbo decoders) and complex correlations for
communication applications.
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit perfor-
mance (based on FIR)
fixed-point (16-bit) operations per cycle, providing
1,800 MFLOPS or 7.3 GOPS performance
programming flexibility