FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 142

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Functional Description
5.12.6.2
5.12.6.3
142
Table 5-40. Sleep Types
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events force the system to a full
on state (S0), although some non-critical subsystems might still be shut off and have to be brought
back manually. For example, the hard disk may be shut off during a sleep state, and have to be
enabled via a GPIO pin before it can be used.
Upon exit from the ICH4-controlled Sleep states, the WAK_STS bit is set. The possible causes of
Wake Events (and their restrictions) are shown in
Sleep Type
•
•
Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully
put the system into the corresponding Sleep state by first going to a C2 state. See
Section 5.12.5
Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no
dependencies on observing Stop-Grant cycles from the processor or on clocks other than the
RTC clock.
S1
S3
S4
S5
Intel
This lowers the processor’s power consumption. No snooping is possible in this state.
ICH4 asserts SLP_S3#. The SLP_S3# signal will control the power to non-critical circuits.
Power will only be retained to devices needed to wake from this sleeping state, as well as to
the memory.
ICH4 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal will shut off the power to the
memory subsystem. Only devices needed to wake from this state should be powered.
Same power state as S4. ICH4 asserts SLP_S3#, SLP_S4# and SLP_S5#.
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for details on going to the C2 state.
ICH4 asserts the STPCLK# signal. It also has the option to assert the CPUSLP# signal.
Table
Comment
5-41.
Intel
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82801DB ICH4 Datasheet