FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 429
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FW82801DB S L66K
Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet
1.FW82801DB_S_L66K.pdf
(587 pages)
Specifications of FW82801DB S L66K
Lead Free Status / RoHS Status
Supplier Unconfirmed
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Intel
®
82801DB ICH4 Datasheet
12:6
Bit
19
18
17
16
15
14
13
5
4
3
2
1
0
SMI on Frame List Rollover — RO. Shadow bit of Frame List Rollover bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in the
SMI on Port Change Detect — RO. Shadow bit of Port Change Detect bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in the
SMI on USB Error — RO. Shadow bit of USB Error Interrupt (USBERRINT) bit in the EHCI_STS
register.
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the
SMI on USB Complete — RO. Shadow bit of USB Interrupt (USBINT) bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the EHCI_STS
SMI on BAR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR is 1, then the host controller will issue an SMI.
SMI on PCI Command Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command is 1, then the host controller will issue an
SMI on OS Ownership Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit is 1, the host controller will
Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit is a 1, the host controller will
SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error is a 1, the host controller will
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit is a 1, the host controller
SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit is a 1, the host controller
SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit is a 1, the host controller will issue an
SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit is a 1, the host controller will
SMI.
issue an SMI.
issue an SMI immediately.
issue an SMI.
will issue an SMI.
will issue an SMI.
SMI immediately.
issue an SMI immediately.
EHCI_STS register.
EHCI_STS register.
EHCI_STS register.
register.
Description
EHCI Controller Registers (D29:F7)
429
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