FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 46

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Signal Description
2.10
46
Table 2-10. Power Management Interface Signals
Power Management Interface
SYS_RESET#
SUS_STAT# /
VRMPWRGD
THRMTRIP#
LAN_RST#
PWRBTN#
RSMRST#
SLP_S3#
SLP_S4#
SLP_S5#
SUSCLK
PWROK
LPCPD#
THRM#
Name
RI#
Type
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Thermal Alarm: This is an active low signal generated by external hardware to
start the hardware clock throttling mode. The signal can also generate an SMI#
or an SCI.
Thermal Trip: When low, THRMTRIP# indicates that a thermal trip from the
processor occurred; the Intel
The ICH4 will not wait for the processor stop grant cycle since the processor
has overheated.
S3 Sleep Control: SLP_S3# is for power plane control. It shuts off power to all
non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or
S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. It shuts power to all
non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.
S5 Sleep Control: SLP_S5# is for power plane control. The signal is used to
shut power off to all non-critical systems when in the S5 (Soft Off) states.
Power OK: When asserted, PWROK is an indication to the ICH4 that core
power and PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, the ICH4 asserts PCIRST#.
NOTE: PWROK must deassert for a minimum of 3 RTC clock periods for the
Power Button: The Power Button causes SMI# or SCI to indicate a system
request to go to a sleep state. If the system is already in a sleep state, this
signal causes a wake event. If PWRBTN# is pressed for more than 4 seconds,
this causes an unconditional transition (power button override) to the S5 state
with only the PWRBTN# available as a wake event. Override occurs even if the
system is in the S1–S4 states. This signal has an internal pull-up resistor.
Ring Indicate: This signal is an input from the modem interface. It can be
enabled as a wake event, and this is preserved across power failures.
System Reset: This pin forces an internal reset after being debounced. The
ICH4 will reset immediately if the SMBus is idle; otherwise, it will wait up to
25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system.
Resume Well Reset: This signal is used for resetting the resume power plane
logic.
LAN Reset: This signal must be asserted at least 10 ms after the resume well
power (VccSus3_3 and VccSus1_5) is valid. When deasserted, this signal is
an indication that the resume well power is stable.
Suspend Status: This signal is asserted by the ICH4 to indicate that the
system will be entering a low power state soon. This can be monitored by
devices with memory that need to switch from normal refresh to suspend
refresh mode. It can also be used by other peripherals as an indication that
they should isolate their outputs that may be going to powered-off planes. This
signal is called LPCPD# on the LPC I/F.
Suspend Clock: Output of the RTC generator circuit to use by other chips for
refresh clock.
VRM Power Good: This should be connected to be the processor’s VRM
Power Good.
ICH4 to fully reset the power and properly generate the PCIRST#
output
®
ICH4 will immediately transition to a S5 state.
Description
Intel
®
82801DB ICH4 Datasheet