FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 419

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

12.1.3
Intel
®
82801DB ICH4 Datasheet
PCICMD—PCI Command Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host Controller
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the ICH4 can act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE) — R/W . This bit controls access to the USB EHCI Memory Space
registers.
0 = Disables this functionality.
1 = Enables accesses to the USB EHCI registers. The Base Address register for USB EHCI should
I/O Space Enable (IOSE) — RO. Reserved as 0.
receive a completion status other than “successful” for one of its DMA-initiated memory reads
on the hub interface (and subsequently on its internal interface).
be programmed before this bit is set.
04
0000h
–
05h
(
EHC) is capable of generating (internally) SERR# when it
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, RO
16 bits
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