FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 149

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.12.9.1
Intel
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
I/O
®
Table 5-46. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
82801DB ICH4 Datasheet
Rds
# of
2
2
2
2
2
2
2
2
6
Access
For other operating systems (e.g., MS-DOS) the BIOS should restore the timer back to 54.6 ms
before passing control to the OS. If the BIOS is entering ALT access mode before entering the
suspend state it is not necessary to restore the timer contents after the exit from ALT access mode.
Write Only Registers with Read Paths in ALT Access Mode
The registers described in
field in the table indicates which register will be returned per access to that port.
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 0 base address low byte
DMA Chan 0 base address high
byte
DMA Chan 0 base count low byte
DMA Chan 0 base count high byte
DMA Chan 1 base address low byte
DMA Chan 1 base address high
byte
DMA Chan 1 base count low byte
DMA Chan 1 base count high byte
DMA Chan 2 base address low byte
DMA Chan 2 base address high
byte
DMA Chan 2 base count low byte
DMA Chan 2 base count high byte
DMA Chan 3 base address low byte
DMA Chan 3 base address high
byte
DMA Chan 3 base count low byte
DMA Chan 3 base count high byte
DMA Chan 0–3 Command
DMA Chan 0–3 Request
DMA Chan 0 Mode: Bits(1:0) = “00”
DMA Chan 1 Mode: Bits(1:0) = “01”
DMA Chan 2 Mode: Bits(1:0) = “10”
DMA Chan 3 Mode: Bits(1:0) = “11”.
Data
Table 5-46
2
have read paths in ALT access mode. The access number
Addr
CCh
CAh
CEh
C4h
C6h
C8h
40h
41h
42h
70h
I/O
Rds
# of
7
1
1
1
2
2
2
2
2
2
Access
1
2
3
4
5
6
7
1
2
1
2
1
2
1
2
1
2
1
2
Timer Counter 1 base count low byte
Timer Counter 1 status, bits [5:0]
Timer Counter 2 status, bits [5:0]
DMA Chan 5 base address high byte
DMA Chan 6 base address high byte
DMA Chan 6 base count high byte
DMA Chan 7 base address high byte
DMA Chan 7 base count high byte
Restore Data
Timer Counter 0 status, bits [5:0]
Timer Counter 0 base count low byte
Timer Counter 0 base count high byte
Timer Counter 1 base count high byte
Timer Counter 2 base count low byte
Timer Counter 2 base count high byte
Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
DMA Chan 5 base address low byte
DMA Chan 5 base count low byte
DMA Chan 5 base count high byte
DMA Chan 6 base address low byte
DMA Chan 6 base count low byte
DMA Chan 7 base address low byte
DMA Chan 7 base count low byte
Functional Description
Data
149