FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 380

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

LPC Interface Bridge Registers (D31:F0)
9.10.4
380
GPO_BLINK—GPO Blink Enable Register
Offset Address:
Default Value:
Lockable:
NOTE: GPIO[18] will blink by default immediately after reset. This signal could be connected to an LED to
24:20, 17:0
31:29, 26,
28:27, 25
19:18
Bit
indicate a failed boot (by programming BIOS to clear GP_BLINK[18] after successful POST).
Reserved
GP_BLINK[n]
is programmed as an input. These bits correspond to GPIO that are in the Resume well, and
will be reset to their default values by RSMRST# or a write to the CF9h register.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
GP_BLINK[n]
is programmed as an input. These bits correspond to GPIO that are in the Core well, and will
be reset to their default values by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
rate of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
rate of approximately once per second. The high and low times are approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
GPIOBASE +18h
0004 0000h
No
—
—
R/W. The setting of these bits will have no effect if the corresponding GPIO
R/W. The setting of these bits will have no effect if the corresponding GPIO
Description
Attribute:
Size:
Power Well:
Intel
R/W
32-bit
See bit description
®
82801DB ICH4 Datasheet