FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 75

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.2.2
5.2.2.1
Intel
®
82801DB ICH4 Datasheet
LAN Controller PCI Bus Interface
As a Fast Ethernet controller, the role of the ICH4 integrated LAN controller is to access
transmitted data or deposit received data. The LAN controller, as a bus master device, will initiate
memory cycles via the PCI bus to fetch or deposit the required data.
To perform these actions, the LAN controller is controlled and examined by the processor via its
control and status structures and registers. Some of these control and status structures reside in the
LAN controller and some reside in system memory. For access to the LAN controller’s Control/
Status Registers (CSR), the LAN controller acts as a slave (in other words, a target device). The
LAN controller serves as a slave also while the processor accesses the EEPROM.
Bus Slave Operation
The ICH4 integrated LAN controller serves as a target device in one of the following cases:
The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The
LAN controller treats accesses to these memory spaces differently.
Control/Status Register (CSR) Accesses
The integrated LAN controller supports zero wait-state single cycle memory or I/O mapped
accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space
to accomplish this. Based on its needs, the software driver will use either memory or I/O mapping
to access these registers. The LAN controller provides four valid Kbytes of CSR space, which
include the following elements:
In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN
controller is the target.
Read Accesses: The processor, as the initiator, drives address lines AD[31:0], the command and
byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. As a slave, the LAN
controller controls the TRDY# signal and provides valid data on each data access. The LAN
controller allows the processor to issue only one read cycle when it accesses the Control/Status
Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait-
states by deasserting IRDY# when it is not ready.
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Processor accesses to the LAN controller System Control Block (SCB) Control/Status
Registers (CSR)
Processor accesses to the EEPROM through its CSR
Processor accesses to the LAN controller PORT address via the CSR
Processor accesses to the MDI control register in the CSR
System Control Block (SCB) registers
PORT register
EEPROM control register
MDI control register
Flow control registers
Functional Description
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