FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 455

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

13.1.13
Intel
®
82801DB ICH4 Datasheet
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset:
Default Value:
Bit
7:3
2
1
0
Reserved
I
0 = SMBus behavior.
1 = The ICH4 is enabled to communicate with I
SMB_SMI_EN — R/W. This bit needs to be set for SMBALERT# to be enabled.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
SMBus Host Enable ( HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit
2
C_EN — R/W.
commands.
Section 5.18.4
needs to be enabled for the SMB Host controller to interrupt or SMI#. Note that the SMB Host
controller will not respond to any new requests until all interrupt requests have been cleared.
40h
00h
(Interrupts / SMI#).
Description
Attribute:
Size:
2
C devices. This will change the formatting of some
SMBus Controller Registers (D31:F3)
R/W
8 bits
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