FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 309
FW82801DB S L66K
Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet
1.FW82801DB_S_L66K.pdf
(587 pages)
Specifications of FW82801DB S L66K
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Intel
®
82801DB ICH4 Datasheet
Bit
7
6
5
4
3
2
1
0
ADLIB_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 388h
MSS_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the MSS range to the LPC interface. This range is selected in the
MIDI_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the
SB16_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the SB16 range to the LPC interface. This range is selected in the
FDD_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the
LPT_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the
COMB_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the
COMA_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
LPC_Sound Decode Range Register.
LPC_Sound Decode Range Register.
LPC_FDD/LPT Decode Range Register.
LPC_FDD/LPT Decode Range Register.
LPC_COM Decode Range Register.
LPC_COM Decode Range Register.
Description
LPC Interface Bridge Registers (D31:F0)
–
38Bh to the LPC interface.
309
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