FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 169

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.15.3.1
5.15.3.2
Intel
®
Table 5-55. UltraATA/33 Control Signal Redefinitions
82801DB ICH4 Datasheet
Signal Descriptions
The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a
number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are
shown in
Write cycles are defined as transferring data from ICH4 to IDE device.
The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by
the ICH4 and is used to request that a transfer be stopped or as an acknowledgment to stop a
request from the IDE device.
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to the
ICH4 (read). It is used by the ICH4 to signal when it is ready to transfer data and to add wait-states
to the current transaction. The DIOR# signal is redefined as STROBE for transferring data from the
ICH4 to the IDE device (write). It is the data strobe signal driven by the ICH4 on which data is
transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to the ICH4
(read). It is the data strobe signal driven by the IDE device on which data is transferred during each
rising and falling edge transition. The IORDY signal is redefined as DMARDY# for transferring
data from the ICH4 to the IDE device (write). It is used by the IDE device to signal when it is ready
to transfer data and to add wait-states to the current transaction.
All other signals on the IDE connector retain their functional definitions during Ultra ATA/33
operation.
Operation
Initial setup programming consists of enabling and performing the proper configuration of ICH4
and the IDE device for Ultra ATA/33 operation. For ICH4, this consists of enabling synchronous
DMA mode and setting up appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is
followed. Once programmed, the drive and ICH4 control the transfer of data via the Ultra ATA/33
protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase,
and a burst termination phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the
transfer, the ICH4 asserts DMACK# signal. When DMACK# signal is asserted, the host controller
drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the ICH4 deasserts STOP, waits
for the IDE device to assert DMARDY#, and then drives the first data word and STROBE signal.
For read cycles, the ICH4 tri-states the DD lines, deasserts STOP, and asserts DMARDY#. The
IDE device then sends the first data word and STROBE.
Signal Definition
Standard IDE
DIOW#
DIOR#
IORDY
Table
5-55. Read cycles are defined as transferring data from the IDE device to the ICH4.
Ultra ATA/33 Read
Cycle Definition
DMARDY#
STROBE
STOP
Ultra ATA/33 Write
Cycle Definition
DMARDY#
STROBE
STOP
Channel Signal
ICH4 Primary
PDIOW#
PIORDY
PDIOR#
Functional Description
ICH4 Secondary
Channel Signal
SDIOW#
SIORDY
SDIOR#
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