FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 373

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

9.9.5
Intel
®
82801DB ICH4 Datasheet
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
15:13
Bit
6:4
12
10
11
9
8
7
Reserved
HUBSERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Intel
NOTE: If this bit is set AND the SERR_EN bit in CMD register (D30:F0, Offset 04h, bit 8) is also
HUBNMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an NMI message via the hub interface. The software must read the memory
HUBSMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an SMI message via the hub interface. The software must read the memory
HUBSCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 received an SCI message via the hub interface. The software must read the memory
BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH4 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
NOTE: On write cycles attempted to the 4-MB lower alias to the BIOS space, the BIOSWR_STS
NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
RTC power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit, or by other means (e.g., a checksum on RTC
RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a
legal value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is
written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until
verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
Reserved
memory controller hub (or its equivalent) to determine the reason for the SERR#.
controller hub (or its equivalent) to determine the reason for the NMI.
controller hub (or its equivalent) to determine the reason for the SMI#.
controller hub (or its equivalent) to determine the reason for the SCI.
This occurs when either:
Setting this bit will cause an SMI# (but not a wake event).
•
•
set, the ICH4 will set the SSE bit in SECSTS register (D30:F0, offset 1Eh, bit 14) AND will
also generate a NMI (or SMI# if NMI routed to SMI#).
will not be set.
®
TCOBASE +04h
0000h
No
The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
Any write is attempted to the BIOS and the BIOSWP bit is also set.
ICH4 received an SERR# message via the hub interface. The software must read the
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/WC, RO
16 bit
Core
(Except bit 7, in RTC)
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