FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 239

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.19.3.1
5.19.4
5.19.5
Intel
®
Figure 5-24. SDIN Wake Signaling
82801DB ICH4 Datasheet
Note: On receipt of wake up signalling from the codec, the digital controller will issue an interrupt if
External Wake Event
Codecs can signal the controller to wake the AC-link, and wake the system using AC_SDIN.
The minimum AC_SDIN wake up pulse width is 1 us. The rising edge of AC_SDIN[0],
AC_SDIN[1] or AC_SDIN[2] causes the ICH4 to sequence through an AC-link warm reset and set
the AC ’97_STS bit in the GPE0_STS register to wake the system. The primary codec must wait to
sample AC_SYNC high and low before restarting BIT_CLK as diagrammed in
codec that signaled the wake event must keep its AC_SDIN high until it has sampled AC_SYNC
having gone high, and then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on
the system’s current power down state. Unless a cold or register reset (a write to the Reset register
in the codec) is performed, wherein the AC ‘97 codec registers are initialized to their default
values, registers are required to keep state during all power down modes.
Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not
occur for a minimum of 4 audio frame times following the frame in which the power down was
triggered. When AC-link powers up, it indicates readiness via the codec ready bit.
AC ’97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_RST# low, BIT_CLK, and
SDOUT will be activated and all codec registers will be initialized to their default power on reset
values. AC_RST# is an asynchronous AC ’97 input to the codec.
AC ’97 Warm Reset
A warm reset will re-activate the AC-link without altering the current codec register values. A
warm reset is signaled by driving AC_SYNC high for a minimum of 1 µs in the absence of
BIT_CLK.
Within normal frames, AC_SYNC is a synchronous AC ’97 input to the codec. However, in the
absence of AC_BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the
generation of a warm reset.
The codec must not respond with the activation of AC_BIT_CLK until AC_SYNC has been
sampled low again by the codec. This will prevent the false detection of a new frame.
enabled. Software will then have to issue a warm or cold reset to the codec by setting the
appropriate bit in the Global Control Register.
BIT_CLK
SDOUT
SDIN
SYNC
prev. frame
prev. frame
slot 12
slot 12
TAG
TAG
Power Down
Write to
Frame
0x20
Data
PR4
Sleep State
Wake Event
Functional Description
TAG
TAG
Figure
New Audio
Frame
Slot 1
Slot 1
5-24. The
Slot 2
Slot 2
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