FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 328

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

LPC Interface Bridge Registers (D31:F0)
9.4.7
9.4.8
328
OCW2—Operational Control Word 2 Register
Offset Address:
Default Value:
Following a part reset or ICW initialization, the controller enters the fully nested mode of
operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI
mode are disabled following initialization.
OCW3—Operational Control Word 3 Register
Offset Address:
Default Value:
Bit
7:5
4:3
2:0
Bit
7
6
5
Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of Interrupt
modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
011 = Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0–L2 Are Used
OCW2 Select — WO. When selecting OCW2, bits 4:3 = 00
Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt level acted upon
when the SL bit is active. A simple binary code, outlined below, selects the channel for the command
to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,
L1 and L0 to 0 is sufficient in this case.
Bits
000
001
010
011
Reserved. Must be 0.
Special Mask Mode (SMM) — WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the
Enable Special Mask Mode (ESMM) — WO.
0 = Disable. The SMM bit becomes a “don't care”.
1 = Enable the SMM bit to set or reset the Special Mask Mode.
system priority structure while the routine is executing, through selective enabling/disabling of
the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning.
Interrupt Level
IRQ0/8
IRQ1/9
IRQ2/10
IRQ3/11
Master Controller
Slave Controller
Bit[4:0]=undefined, Bit[7:5]=001
Master Controller
Slave Controller
Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
–
Bits
100
101
110
111
–
0A0h
0A0h
–
–
020h
020h
Interrupt Level
IRQ4/12
IRQ5/13
IRQ6/14
IRQ7/15
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
WO
8 bits
WO
8 bits
®
82801DB ICH4 Datasheet