FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 434

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

EHCI Controller Registers (D29:F7)
12.2.1.4
434
HCCPARAMS—Host Controller Capability Parameters Register
Offset:
Default Value:
31:16
15:8
Bit
7:4
3
2
1
0
Reserved
EHCI Extended Capabilities Pointer (EECP) — RO. Hardwired to 68h, indicating that the EHCI
capabilities list exists and begins at offset 68h in the PCI configuration space.
Isochronous Scheduling Threshold — RO. Hardwired to 7h (0111). This field indicates, relative to the
current position of the executing host controller, where software can reliably update the isochronous
schedule.
When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host
controller hold a set of isochronous data structures (one or more) before flushing the state.
When bit 7 is a 1, host software assumes the host controller may cache an isochronous data
structure for an entire frame. Refer to the EHCI specification for details on how software uses this
information for scheduling isochronous transfers.
Reserved. Should be set to 0.
Asynchronous Schedule Park Capability — RO. Hardwired to 0, indicating that the Host controller
does not support this optional feature
Programmable Frame List Flag — RO.
0 = System software must use a frame list length of 1024 elements with this host controller. The
1 = System software can specify and use a smaller frame list and configure the host controller via
64-bit Addressing Capability— RO. Hardwired to 1. This field documents the addressing range
capability of this implementation. The value of this field determines whether software should use the
32-bit or 64-bit data structures. Values for this field have the following interpretation:
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
NOTE: The ICH4 only implements 44 bits of addressing. Bits 63:44 will always be 0.
USBCMD register Frame List Size field is a read-only register and must be set to zero.
the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K page
boundary. This requirement ensures that the frame list is always physically contiguous.
08
00006871h
–
0Bh
Description
Attribute:
Size:
RO
32 bits
Intel
®
82801DB ICH4 Datasheet