MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 106

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Bus Operation
nous input setup and hold times around the end of S2. If wait states are added, the QUICC
continues to sample DSACKx on the falling edges of the clock until one is recognized.
State 4—At the end of S4, the QUICC latches the incoming data.
State 5—The QUICC negates OE, AS, and DS during S5. If more than one read cycle is
required to read in the operand(s), S0–S5 are repeated for each read cycle. When finished
reading, the QUICC holds the address, R/W, and FC3–FC0 valid in preparation for the write
portion of the cycle. The external device keeps its data and DSACKx signals asserted until
it detects the negation of AS or DS (whichever it detects first). The device must remove the
data and negate DSACKx within approximately one clock period after sensing the negation
of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely
detected for the next portion of the operation.
Idle States—The QUICC does not assert any new control signals during the idle states, but
it may internally begin the modify portion of the cycle at this time. S0–S5 are omitted if no
write cycle is required. If a write cycle is required, R/W remains in the read mode until S0 to
prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven
until S2.
State 0—The QUICC drives R/W low for a write cycle. Depending on the write operation to
be performed, the address lines may change during S0.
State 1—In S1, the QUICC asserts AS, indicating a valid address on the address bus. Dur-
ing this state, WE0, WE1, WE2, and/or WE3 assert simultaneously with AS.
State 2—During S2, the QUICC places the data to be written onto D31–D0.
State 3—The QUICC asserts DS during S3, indicating stable data on the data bus. As long
as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asyn-
chronous input setup time requirement), the cycle terminates one clock later. If DSACKx is
not recognized by the start of S3, the QUICC inserts wait states instead of proceeding to S4
and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain
negated throughout the asynchronous input setup and hold times around the end of S2. If
wait states are added, the QUICC continues to sample DSACKx on the falling edges of the
clock until one is recognized. The selected device uses WE3–WE0 or R/W, DS, SIZ1, SIZ0,
A1, and A0 to latch data from the appropriate section(s) of the data bus (D31–D24, D23–
D16, D15–D8, and D7–D0). WE3–WE0 or SIZ1, SIZ0, A1, and A0 select the data bus sec-
tions. If it has not already done so, the device asserts DSACKx when it has successfully
stored the data.
State 4—The QUICC issues no new control signals during S4.
State 5—The QUICC negates WE3–WE0, AS, and DS during S5. It holds the address and
data valid during S5 to provide address hold time for memory systems. R/W and FC3–FC0
also remain valid throughout S5. If more than one write cycle is required, S0–S5 are
repeated for each write cycle. The external device keeps DSACKx asserted until it detects
the negation of AS or DS (whichever it detects first). The device must remove its data and
4-30
MC68360 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com