MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 584

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
E—Empty
Bits 14, 9–6—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Frame
F—First in Frame
M—Miss
7-260
This bit is set by the Ethernet controller when this buffer is the last in a frame. This implies
the end of the frame or reception of an error, in which case one or more of the CL, OV,
CR, SH, NO, and LG bits are set. The Ethernet controller will write the number of frame
octets to the data length field.
This bit is set by the Ethernet controller when this buffer is the first in a frame.
This bit is set by the Ethernet controller for frames that were accepted in promiscuous
mode, but were flagged as a "miss" by the internal address recognition. Thus, while in pro-
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this Rx BD has been filled with received data, or
1 = The data buffer associated with this Rx BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been used.
1 = The RXB bit or RXF bit in the Ethernet event register will be set when this buffer
0 = The buffer is not the last in a frame.
1 = The buffer is the last in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BD s in this table is programmable and is determined only by
the W-bit and the overall space constraints of the dual-port RAM.
has been used by the Ethernet controller. These two bits may cause interrupts if
they are enabled.
15
E
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
11
L
Go to: www.freescale.com
10
F
RX DATA BUFFER POINTER
—
9
DATA LENGTH
—
8
—
7
—
6
LG
5
NO
4
SH
3
CR
2
OV
1
CL
0