MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 468

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
The receiver uses a clock 8, 16, or 32 times faster then the baud rate and samples each bit
of the incoming data three times around its center. The value of the bit is determined by the
majority of those samples. If the samples do not all agree, a noise indication counter is incre-
mented. When a complete byte has been clocked in, the contents of the shift register are
transferred to the UART receive data register. If there is an error in this character, then the
appropriate error bits will be set by the CP.
The UART may receive fractional stop bits. The next character’s start bit may begin anytime
after the three middle samples have been taken.
The UART transmit shift register transmits the outgoing data on the TXDx pin. Data is
clocked synchronously with the transmit clock, which may have either an internal or external
source. The order of bit transmission is LSB first.
Only the data portion of the UART frame is actually stored in the data buffers. The start and
stop bits are always generated and stripped by the UART controller. The parity bit may also
be generated in transmission and checked during reception. Although parity is not stored in
the data buffer, its value may be inferred from the reporting mechanism in the data buffer
(i.e., character with parity errors are identified). Similarly, the optional address bit is not
stored in the transmit or receive data buffer, but is implied from the buffer descriptor itself.
Parity is generated and checked for the address bit, when present.
The RFW bit in the GSMR must be set for an 8-bit receive FIFO for the UART receiver.
7.10.16.3 SYNCHRONOUS MODE. In synchronous mode, the UART controller uses the 1
data clock for timing. The receive shift register receives the incoming data on the RXD pin
synchronously to the clock. The length and format of the serial word in bits are defined by
the control bits in the UART mode register in the same manner as for asynchronous mode.
When a complete byte has been clocked in, the contents of the shift register are transferred
to the UART receive data register. If there is an error in this character, then the appropriate
error bits will be set by the CP.
The UART transmit shift register transmits the outgoing data on the TXD pin. Data is clocked
synchronously with the transmit clock, which may have either an internal or external source.
The RFW bit in the GSMR must be set for an 8-bit receive FIFO for the UART receiver.
7-144
1. Start Bit
2. 5–8 Data Bits (LSB first)
3. Address/Data Bit (optional)
4. Parity Bit (optional)
5. Stop Bits
of the UART character is defined by the control bits in the UART mode register. The
order of reception is:
Freescale Semiconductor, Inc.
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