MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 561

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

7.10.23.2 ETHERNET KEY FEATURES. The Ethernet contains the following key features:
CTS = CLSN
CD = RENA
• Performs MAC Layer Functions of Ethernet and IEEE 802.3
• Performs Framing Functions
• Full Collision Support
• Bit Rates up to 10 Mbps
• Receives Back-to-Back Frames
• Detection of Receive Frames That Are Too Long
• Multibuffer Data Structure
• Supports 48-Bit Addresses in Three Modes:
RSTRT
RRJCT
—Preamble Generation and Stripping
—Destination Address Checking
—RC Generation and Checking
—Automatic “Short Frames” Padding on Transmit
—Framing Error (Dribbling Bits) Handling
—Enforces the Collision (Jamming)
—Truncated Binary Exponential Backoff Algorithm for Random Wait
—Two Nonaggressive Backoff Modes
—Automatic Frame Retransmission (Until “Attempt Limit” Is Reached)
—Automatic Discard of Incoming Collided Frames
—Delay Transmission of New Frames for Specified Interframe Gap
PERIPHERAL BUS
IMB
RECEIVER
CONTROL
RXD
UNIT
Freescale Semiconductor, Inc.
Figure 7-66. Ethernet Block Diagram
For More Information On This Product,
MC68360 USER’S MANUAL
RECEIVE
SHIFTER
Go to: www.freescale.com
DATA
FIFO
REGISTERS
CONTROL
TRANSMIT
SHIFTER
DATA
FIFO
Serial Communication Controllers (SCCs)
TRANSMITTER
CONTROL
UNIT
TXD
INTERNAL CLOCKS
GENERATOR
AND DEFER
SLOT TIME
COUNTER
CLOCK
RTS = TENA
CD = RENA
CTS = CLSN
TX CLOCK
RX CLOCK