MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 451

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

FC3–FC0—Function Code 3–0
7.10.7.3 MAXIMUM RECEIVE BUFFER LENGTH REGISTER (MRBLR). Each SCC has
one MRBLR to define the receive buffer length for that SCC. MRBLR defines the maximum
number of bytes that the QUICC will write to a receive buffer on that SCC before moving to
the next buffer. The QUICC may write fewer bytes to the buffer than MRBLR if a condition
such as an error or end-of-frame occurs, but it will never write more bytes than the MRBLR
value. It follows, then, that buffers supplied by the user for use by the QUICC should always
be of size MRBLR (or greater) in length.
The transmit buffers for an SCC are not affected in any way by the value programmed into
MRBLR. Transmit buffers may be individually chosen to have varying lengths, as needed.
The number of bytes to be transmitted is chosen by programming the data length field in the
Tx BD.
7.10.7.4 RECEIVER BD POINTER (RBPTR). The RBPTR for each SCC channel points to
the next BD that the receiver will transfer data to when it is in idle state or to the current BD
during frame processing. After a reset or when the end of the BD table is reached, the CP
initializes this pointer to the value programmed in the RBASE entry. Although RBPTR need
never be written by the user in most applications, it may be modified by the user when the
receiver is disabled or when the user is sure that no receive buffer is currently in use.
7.10.7.5 TRANSMITTER BD POINTER (TBPTR). The TBPTR for each SCC channel
points to the next BD that the transmitter will transfer data from when it is in idle state or to
the current BD during frame transmission. After a reset or when the end of the BD table is
reached, the CP initializes this pointer to the value programmed in the TBASE entry.
These bits contain the function code value used during this SDMA channel’s memory ac-
cesses. It is suggested that the user write bit FC3 with a one to identify this SDMA channel
access as a DMA-type access. Example: FC3–FC0 = 1000 (binary). Do not write the val-
ue 0111 (binary) to these bits.
MRBLR is not intended to be changed dynamically while an
SCC is operating. However, if it is modified in a single bus cycle
with one 16-bit move (NOT two 8-bit bus cycles back-to-back),
then a dynamic change in receive buffer length can be success-
fully achieved. This takes place when the CP moves control to
the next Rx BD in the table. Thus, a change to MRBLR will not
have an immediate effect. To guarantee the exact Rx BD on
which the change will occur, the user should change MRBLR
only while the SCC receiver is disabled.
The MRBLR value should be greater than zero for all modes.
For Ethernet and HDLC the MRBLR should be evenly divisible
by 4. In totally transparent mode, MRBLR should also be divisi-
ble by 4, unless the receive FIFO width (RFW) bit in GSMR is set
to 8 bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)