MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 193

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that
faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32+
defines four fault types: released write faults, faults during exception processing, faults dur-
ing MOVEM operand transfer, and faults on any other bus cycle.
5.5.3.1.1 Type I—Released Write Faults. CPU32+ instruction pipelining can cause a final
instruction write to overlap the execution of a following instruction. A write that is overlapped
is called a released write. A released write fault occurs when a bus error or some other fault
occurs on the released write.
Released write faults are taken at the next instruction boundary. The stacked PC is that of
the next unexecuted instruction. If a subsequent instruction attempts an operand access
while a released write fault is pending, the instruction is aborted and the write fault is
acknowledged. This action prevents the instruction from using stale data.
The SSW for a released write fault contains the following bit pattern:
TR , B1, and B0 are set if the corresponding exception is pending when the bus error excep-
tion is taken. Status regarding the faulted bus cycle is reflected in the SZCx, SIZ, and FUNC
fields.
The remainder of the stack contains the PC of the next unexecuted instruction, the current
SR, the address of the faulted memory location, and the contents of the data buffer that was
to be written to memory. This data is written on the stack in the format depicted in Figure 5-
15. When a released write fault exception handler executes, the machine will complete the
faulted write and then continue executing instructions wherever the PC indicates.
5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus
error exceptions are included in this category—all instruction prefetches, all operand reads,
all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the
last write of a MOVEP Rn, ea or the last write of MOVEM, which are type I faults). The TAS,
MOVEP, and MOVEM instructions account for all operand writes not considered released
write faults.
All type II faults cause an immediate exception that aborts the current instruction. Any reg-
isters that were altered as the result of an EA calculation (i.e., postincrement or predecre-
ment) are restored prior to processing the bus cycle fault.
The SSW for faults in this category contains the following bit pattern:
The trace pending bit is always cleared since the instruction will be restarted upon return
from the handler. Saving a pending exception on the stack causes a trace exception to be
15
15
0
0
14
14
0
0
SZC1
SZC1
13
13
TR
12
12
0
Freescale Semiconductor, Inc.
11
B1
11
B1
For More Information On This Product,
B0
B0
10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
1
9
0
RM
8
0
8
IN
7
0
7
RW
6
0
6
SZC0
SZC0
5
5
4
4
SIZ
SIZ
3
3
2
2
FUNC
FUNC
CPU32+
0
0