MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 765

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
9.4.2.7 EEPROM. Figure 9-14 shows the interface to an EEPROM device to give a small
amount of nonvolatile storage. Although both the MC68EC040 and the QUICC may access
the EEPROM, it is most likely that only the MC68EC040 will access the EEPROM. The
inverter is only required if DRAM is used elsewhere in the system, since the OE function is
lost when the AMUX pin is used.
The EEPROM device sits on just the D7–D0 data pins. Thus, when the MC68EC040
accesses the EEPROM, the only valid data that is read or written is on the D7–D0 pins (i.e.,
byte 3). Thus, reads or writes to successive locations of the EEPROM will require the
address to be incremented by 4 each time. Additionally, the CS4 pin should be programmed
to respond to a full 32-Kbyte area, even though only 8 Kbytes are present.
After a write is made, software is responsible for waiting the appropriate time (e.g., 10 ms)
or for performing data polling to see if the newly written data byte is correct.
9.4.2.8 DRAM SIMM. Figure 9-15 shows the interface to an MCM36100S DRAM single in-
line memory module (SIMM). Both the MC68EC040 and the QUICC can access the DRAM.
When the QUICC is a slave to an external MC68EC040, the address multiplexing for the
DRAM must be done externally to the QUICC, which is accomplished in the three F157 mul-
tiplexers. The external address multiplexing scheme was chosen to allow the QUICC to pro-
vide burst accesses by the MC68EC040, using the BADD3–BADD2 pins. The QUICC can
also use these pins as its A3–A2 address lines during its own accesses to the DRAM. In
addition, two of the multiplexer outputs are unused in this design, allowing expansion to
9-45
Figure 9-14. 8-Kbyte EEPROM Bank—8 Bits Wide
A14–A2
SYSTEM BUS AND
QUICC-GENERATED SIGNALS
D7–D0
CS4
R/W
WE3
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE (Enable)
OE
WE (Write)
LOW-ORDER
EEPROM
8K 8
BYTE 3
2864
BYTE
A10
A12
A11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9