MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 797

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Applications
It is important for the designer to distinguish the difference between an MC68EC030 access-
ing memory synchronously and the QUICC memory controller operating in synchronous
mode. The MC68EC030 has the ability to access memory in standard asynchronous bus
cycles (i.e., three clocks or longer) and synchronous bus cycles (two clocks). For
MC68EC030 asynchronous accesses, the QUICC memory controller can generate chip
selects, DSACKx, etc. However, the QUICC does not support MC68EC030 synchronous
bus cycles (nor does it support MC68EC030 bursting). This does not mean that the
MC68EC030 cannot perform two-clock accesses in a QUICC system—only that the QUICC
will not assist (i.e., generate chip selects, etc.) during these accesses.
The QUICC memory controller can operate asynchronously or synchronously (defined by
the BSTM bit in the MCR and the SYNC bit in the GMR). When the QUICC memory control-
ler is operating synchronously, the external signals being monitored are not synchronized
internally by the QUICC, and must be provided with the proper setup and hold times. When
the synchronous function is not enabled, externally generated bus signals are latched on the
negative edge of the QUICC clock before being recognized, permitting external signals to
be completely asynchronous to the QUICC clock. The QUICC memory controller is normally
used in synchronous mode with the MC68EC030, even if the MC68EC030 is generating
only asynchronous bus cycles.
The QUICC clocking section allows for the clock oscillator to be kept running through the
VDDSYN pin in a power-down situation, if desired. Low-power issues are not addressed.
9.8.1.3 RESET STRATEGY. If a QUICC is configured to provide the global chip select, it will
also provide an internal power-on reset generation. Thus, the RESETH pin of the QUICC
just needs to be connected to the RESET pin on the MC68EC030. If a pushbutton switch is
needed, it can be connected by an open-drain buffer to the RESET line, once debounced.
9.8.1.4 INTERRUPTS. External interrupts may be brought into the QUICC through either
the IRQx pins or parallel I/O pins. The QUICC prioritizes these interrupts with its own inter-
nally generated interrupts (e.g., timers) to obtain the current highest pending request. In
slave mode, the QUICC can output this request to another processor in the system.
The request can take the form of a single request pin or three request pins (IOUT2–IOUT0)
that encode the priority of the request. Since the MC68EC030 uses encoded inputs (IPL2–
IPL0), the IOUT2–IOUT0 pins are chosen.
In addition, the QUICC allows the IOUT2–IOUT0 pins to be generated in two different ways:
at the expense of parity pins or at the expense of some interrupt requests. In this application,
parity is not used in the system; thus, the parity pins are chosen for this function, leaving
more interrupt pins available.
Once the MC68EC030 recognizes the interrupt, it responds with an interrupt acknowledge
cycle. The QUICC recognizes the MC68EC030 interrupt acknowledge cycle using the
address and function code pins (FC3–FC0). The QUICC then responds by placing the vec-
tor on the bus or by outputting the AVECO signal to the MC68EC030, depending on what
was programmed into the autovector register in the SIM60.
9-77
MC68360 USER’S MANUAL
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