MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 381

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
SDMA Channels
7.7 SDMA CHANNELS
Fourteen SDMA channels are present on the QUICC. Eight are associated with the four full-
duplex SCCs. The other six are assigned to the service of the SPI and the two SMCs. Each
channel is permanently assigned to service either the receive or transmit operation of an
SCC, SMC, or SPI.
Figure 7-17 shows the paths of the data flow. Data from the SCCs, SMCs, and SPI may be
routed to the external RAM (path 1) or the internal dual-port RAM (path 2). In both cases,
however, the IMB is used for the data transfer. On a path 1 access, the IMB and the external
system bus must be acquired by the SDMA channel. On a path 2 access, only the IMB
needs to be acquired, and the access will not be seen on the external system bus unless
the QUICC is configured into the "show cycles" mode of the SIM60. Thus, the transfer on
the IMB can occur while other operations occur simultaneously on the external system bus.
Each SDMA channel may be programmed to output one of 16 function codes. The function
codes are used to identify the channel that is currently accessing memory. Also, the SDMA
channel may be assigned a big endian (Motorola) or little endian format for accessing buffer
data. These features are programmed in the receive and transmit function code registers
associated with the SCCs, SMCs, and SPI.
If a bus error occurs on an access by the SDMA, the CPM generates a unique interrupt in
the SDMA status register. The interrupt service routine then reads the SDMA address reg-
ister to determine the address on which the bus error occurred. The channel that caused the
bus error is determined by reading the Rx internal data pointer and Tx internal data pointers
from the specific protocol parameters area in the parameter RAM for the serial channels. If
an SDMA bus error occurs, all CP activity ceases, and the entire CP must be reset in the
command register.
7.7.1 SDMA Bus Arbitration and Bus Transfers
On the QUICC, the SDMA, IDMA, and DRAM refresh controller can become internal bus
masters. To determine the relative priority of these masters, each is given an arbitration ID.
The 14 SDMA channels share the same ID, which is programmed by the user. Therefore,
any SDMA channel can arbitrate for the bus against the other internal masters and any
external masters that are present.
Once an SDMA channel obtains the system bus, it remains the bus master for one long-
word transfer before relinquishing the bus. This feature, in combination with the zero clock
arbitration overhead provided by the IMB, allows the simultaneous benefits of bus efficiency
and low bus latency.
In the case of character-oriented protocols, the SDMA writes characters to memory (it does
not wait for multiple characters to be received before writing), but the SDMA always reads
long words. This is consistent with the goal of providing low-latency operation on character-
oriented protocols that tend to be used at slower rates.
MC68360 USER’S MANUAL
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