MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 593

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Refer to Figure 7-73 for the SMC block diagram. The SMC receiver and transmitter are dou-
ble-buffered, as shown in the block diagram. This corresponds to an effective FIFO size
(latency) of two characters.
The receive data source for an SMC can be either the L1RXD pin if the SMC is connected
to a TDM channel of the SI, or the SMRXD pin if the SMC is connected to the NMSI. The
transmit data source can either be the L1TXD pin if the SMC is connected to a TDM, or the
SMTXD pin if the SMC is connected to the NMSI.
If the SMC is connected to a TDM, the SMC receive clock and SMC transmit clock can be
independent from each other as defined in the SI description. However, if the SMC is con-
nected to the NMSI, the SMC receive clock and SMC transmit clock must be connected to
a single clock source called SMCLK. SMCLK is an internal signal name for a clock that is
generated from the bank of clocks defined in the SI description. SMCLK may originate from
an external pin or one of the four internal baud rate generators. See 7.8.9 NMSI Configura-
tion for more details.
If the SMC is connected to a TDM, it derives its synchronization pulse from the TSA as
defined in the SI description. Otherwise, if the SMC is connected to the NMSI and the totally
transparent protocol is selected, the SMC may use the SMSYN pin as a synchronization pin
to determine when transmission and reception should begin. (The SMSYN pin is not used
in the SMC UART mode.)
T_ DATA_ REGISTER
TRANSMITTER
PAR TO SER
TX DATA
PERIPHERAL BUS
Freescale Semiconductor, Inc.
MODE _REGISTER
For More Information On This Product,
Figure 7-73. SMC Block Diagram
R_ DATA_ REGISTER
MC68360 USER’S MANUAL
SER TO PAR
Go to: www.freescale.com
RECEIVER
RX DATA
IMB
CONTROL
Serial Management Controllers (SMCs)
RX CLOCK
TX CLOCK
TO L1TXD IN SI OR SMTXD
FROM L1RXD IN SI OR SMRXD
SYNC
FROM SI OR SMSYN
FROM SI OR SMCLK
FROM SI OR SMCLK