MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 372

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

IDMA Channels
IDMA channel 1 initialization required for this example:
7.6.4.6.2 Single Address Mode (Flyby Transfers). Each IDMA channel can be indepen-
dently programmed to provide single address transfers. Figure 7-14 illustrates a transfer
from memory to a peripheral. The DHR is not used by the IDMA, since the transfer occurs
directly from a device to memory. This mode is often referred to as "flyby" mode because
the DHR is not used.
7-48
• ICCR = $0720. Recommended normal configuration.
• FCR1 = $89. Source function code is 1000; destination function code is 1001.
• SAPR1 = $00000002. Source address.
• DAPR1 = $20000002. Destination address.
• BCR1 = $00000008. Byte transfer count.
• CSR1 = $FF. Clear any CSR bits that are currently set.
• CMAR1 = $00. Disable interrupts for this example.
• CMR1 = $4711. Internal maximum transfer rate; starts IDMA.
Bus Access #
10
11
1
2
3
4
5
6
7
8
9
Figure 7-14. Single Address Transfer Example
Freescale Semiconductor, Inc.
QUICC
Address (Hex)
IDMA
For More Information On This Product,
$00000002
$20000002
$20000003
$00000004
$20000004
$20000005
$20000006
$20000007
$00000008
$20000008
$20000009
MC68360 USER’S MANUAL
Go to: www.freescale.com
ADDR.
DACKx
JUST ONE BUS CYCLE
REQUIRED
Operation
DATA
BUS
Read
Write
Write
Read
Write
Write
Write
Write
Read
Write
Write
1
1
No. Bytes
2
1
1
4
1
1
1
1
2
1
1
PERIPHERAL
MEMORY
No. Bytes in DHR
2
1
0
4
3
2
1
0
2
1
0