MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 773

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
9.5.3 MC68EC040 Cache Behavior
To better understand the cache operation of the MC68EC040, the following brief explana-
tion describes how the MC68EC040 caches and access control unit work. When the
MC68EC040 comes out of reset, the caches and access control units are disabled, and all
accesses are in cache-inhibited, nonserialized mode. When the caches are first enabled,
the information in the cache is unknown; therefore, it is important to invalidate the caches
before enabling them. The caches are enabled by accessing the cache access control reg-
ister (CACR). The data access control unit is enabled by enabling one or both of the data
access control registers (DAC0 and DAC1). When a data access is made, the MC68EC040
compares the upper eight bits of the address to the base address and address mask of the
enabled data access control registers. An address match with the data access control reg-
ister occurs if the upper eight bits of the access address matches the base address or is
masked off by the data access control register address mask. If the address does not match
either data access control register, the caching mode is the default (cache-inhibited, nonse-
rialized if the cache is disabled or write-through if the cache is enabled). If the address does
match one of the data access control registers, the cache mode bits of the matching data
access control register select the caching mode. If both data access control registers match,
DAC0 takes priority over DAC1. The instruction accesses work the same, except the instruc-
tion access control unit is used.
9.5.4 Enabling the Caching Modes
To enable the multiple caching modes, enable DAC0 and IAC0 for cache-inhibited, serial-
ized (cache mode bits = 10), mask out (set to ones) all but two address bits, and set the
remaining two address bits to the cache-inhibited, serialized region (e.g., address bits = 00).
Enable DAC1 and IAC1 for cachable, copyback (cache mode bits = 01), mask out (set to
ones) all but two address bits, and set the remaining two address bits to the cache-inhibited,
copyback region (e.g., address bits = 01). The write protect bit, user page attribute bits, and
function code bits are set as the user requires for both DAC0 and DAC1. When the caches
are enabled, all accesses in which the nonmasked address bits are 00 use DAC0 or IAC0
and are cache-inhibited, serialized. All accesses in which the nonmasked address bits are
01, use DAC1 or IAC1 and are cachable, copyback. All accesses in which the nonmasked
address bits do not match either access control register are not affected by the access con-
trol units and default to cachable, write-through.
The following MC68EC040 code is used for enabling the access control unit for this caching
scheme:
9-53
MOVE.LD0, –(A7)
CINVABC
MOVE.L#$80008000,D0
MOVECD0,CACR
MOVE.L#$003FC020,D0
MOVECD0, DAC0
MOVECD0, IAC0
MOVE.L#$403FC010,D0
MOVECD0, DAC1
MOVECD0, IAC1
MOVE.L(A7)+,D0
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com