MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 187

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Exception processing for privilege violations is nearly identical to that for illegal instructions.
The instruction is fetched and decoded. If the processor determines that a privilege violation
has occurred, exception processing begins before instruction execution.
Exception processing follows the regular sequence. The vector number (8) is generated to
reference the privilege violation vector. Privilege violation vector offset, current PC, and SR
are saved on the supervisor stack. The saved PC value is the address of the first word of
the instruction causing the privilege violation.
5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility
to allow tracing of instruction execution. CPU32+ tracing also has the ability to trap on
changes in program flow. In trace mode, a trace exception is generated after each instruc-
tion executes, allowing a debugging program to monitor the execution of a program under
test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing.
When T1–T0 = 00, tracing is disabled, and instruction execution proceeds normally (see
Table 5-18).
When T1–T0 = 01 at the beginning of instruction execution, a trace exception will be gener-
ated if the PC changes sequence during execution. All branches, jumps, subroutine calls,
returns, and SR manipulations can be traced in this way. No exception occurs if a branch is
not taken.
When T1–T0 = 10 at the beginning of instruction execution, a trace exception will be gener-
ated when execution is complete. If the instruction is not executed, either because an inter-
rupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception
is not generated.
• MOVE to SR
• MOVE USP
• MOVEC
• MOVES
• OR Immediate to SR
• RESET
• RTE
• STOP
Freescale Semiconductor, Inc.
For More Information On This Product,
T1
0
0
1
1
Table 5-18. Tracing Control
MC68360 USER’S MANUAL
Go to: www.freescale.com
T0
0
1
0
1
No tracing
Trace on change of flow
Trace on instruction execution
Undefined; reserved
Tracing Function
CPU32+