MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 475

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

E—End of Table
R—Reject Character
CHARACTER1–8—Control Character Values
RCCM—Received Control Character Mask
RCCR—Received Control Character Register
7.10.16.9 WAKE-UP TIMER (RECEIVER). By issuing the ENTER HUNT MODE command,
the user can temporarily disable the UART receiver. It will remain inactive until an idle or
address character is recognized (depending on the setting of the UM bits).
If the UART is still in the process of receiving a message that the user has already decided
to discard, the user may abort its reception by issuing the ENTER HUNT MODE command.
The UART receiver will be reenabled when the message is finished by detecting the idle line
(one character of idle) or by the address bit of the next message, depending on the UM bits.
When the receiver is in sleep mode and a break sequence is received, the receiver will incre-
ment the BRKEC counter and generate the BRK interrupt if it is enabled.
7.10.16.10 BREAK SUPPORT (RECEIVER). The UART offers very flexible break support
for the receiver.
In tables with 8 control characters, E is always zero.
These fields define control characters that should be compared to the incoming character.
For less than 8-bit characters, the MSB should be zero.
The value in this register is used to mask the comparison of CHARACTER1–8. The lower
eight bits of RCCM correspond to the lower eight bits of CHARACTER1–8 and are decod-
ed as follows:
Bits 15 and 14 of RCCM must be set, or erratic operation may occur during the control
character recognition process.
Upon a control character match for which the reject bit is set, the UART will write the con-
trol character into the RCCR and generate a maskable interrupt. The CPU32+ core must
process the interrupt and read the RCCR before a second control character arrives. Fail-
ure to do so will result in the UART overwriting the first control character.
0 = This entry is valid. The lower 8 bits will be checked against the incoming character.
1 = The entry is not valid. This must be the last entry in the control characters table.
0 = The character is not rejected but is written into the receive buffer. The buffer is then
1 = If this character is recognized, it will not be written to the receive buffer. Instead, it
0 = Mask this bit in the comparison of the incoming character and CHARACTER1–8.
1 = The address comparison on this bit proceeds normally; no masking occurs.
closed, and a new receive buffer is used if there is more data in the message. A
maskable (I-bit in the Rx BD) interrupt is generated.
is written to the RCCR, and a maskable interrupt is generated. The current buffer
is not closed when a control character is received with R set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)