MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 627

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

RX—Rx Buffer
7.11.10.14 SMC TRANSPARENT MASK REGISTER (SMCM). The SMCM is referred to
as the SMC transparent mask register when the SMC is operating in transparent mode. It is
an 8-bit read-write register that has the same bit format as the transparent event register. If
a bit in the SMCM is a one, the corresponding interrupt in the transparent event register will
be enabled. If the bit is zero, the corresponding interrupt in the transparent event register
will be masked. This register is cleared upon reset.
7.11.11 SMC Transparent NMSI Example
The following list is an initialization sequence for operation of the SMC1 transparent channel
over its own set of pins. The transmit and receive clocks are provided from the CLK3 pin (no
baud rate generator is used), and the SMSYNx pin is used to obtain synchronization. (The
SMC UART example shows an example of configuring the baud rate generator.)
that the data was completely sent over the transmit pin. If the L-bit of the Tx BD is cleared,
this bit is set when the last data character is written to the transmit FIFO; the user must
wait two character times to be sure that the data was completely sent over the transmit
pin.
A buffer has been received on the SMC channel and its associated Rx BD is now closed.
This bit is set after the last character was written to the buffer.
1. The SDCR (SDMA Configuration Register) should be initialized to $0740, rather than
2. Configure the port B pins to enable the SMTXD1, SMRXD1, and SMSYN1. Write
3. Configure the port A pins to enable CLK3. Write PBPAR bit 10 and PADIR bit 10 with
4. Connect the CLK3 clock to SMC1 using the SI. Write the SMC1 bit in SIMODE with
5. Write RBASE and TBASE in the SMC parameter RAM to point to the Rx BD and Tx
6. Program the CR to execute the INIT RX & TX PARAMS command for this channel."
7. Write RFCR with $18 and TFCR with $18 for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
9. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
being left at its default value of $0000.
PBPAR bits 6, 7, and 8 with ones. Write PBDIR bits 6, 7, and 8 with zeros. Write
PBODR bits 6, 7, and 8 with zeros.
a one. Write PBDIR bit 10 with a zero. The other functions of this pin are the timers or
the TSA.
These alternate functions cannot be used on this pin.
a 0. Write the SMC1CS bits in SIMODE with 110.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 16 bytes, so MRBLR = $0010.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Management Controllers (SMCs)