MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 766
MC68EN360AI25VL
Manufacturer Part Number
MC68EN360AI25VL
Description
Manufacturer
Freescale
Datasheet
1.MC68EN360AI25VL.pdf
(962 pages)
Specifications of MC68EN360AI25VL
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Compliant
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MC68EN360AI25VL
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Applications
future 16M
36 DRAM SIMMs. In fact, this multiplexing scheme allows SIMMs of many dif-
ferent sizes to be used on the board without hardware modification.
This particular SIMM also includes parity support, supported with the PRTY3–PRTY0 sig-
nals.
This design also uses the RAS1 double-drive capability, whereby the RAS1DD signal is out-
put by the QUICC to increase the effective drive capability of the RAS1 signal. The RAS1
line should be programmed to respond to a 4-Mbyte address space.
After power-on reset, the software must wait the required time before accessing the DRAM.
The required eight read cycles must then be performed either in software or by waiting for
the refresh controller to perform these accesses.
9.4.2.9 DRAM DEVICES. Figure 9-16 shows the interface to a standalone DRAM device. In
this case, the MCM54260 256K
16 DRAM device is chosen. This allows a full 32-bit-wide
DRAM solution using only two DRAM devices, with byte writes still supported using the
upper and lower CASx pins. Both the MC68EC040 and the QUICC can access the DRAM
array. The RAS1 line should be programmed to respond to a 1-Mbyte address space.
The address multiplexing scheme is the same as that for the DRAM SIMM. No parity support
is provided in this case. The RAS1DD signal is not used in this case since only two devices
are supported.
After power-on reset, the software must wait the required time before accessing the DRAM
(approximately 100 s). The required eight read cycles must then be performed either in
software or by waiting for the QUICC refresh controller to perform these accesses.
9-46
MC68360 USER’S MANUAL
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